This graph of the EEMBC CoreMark-Pro benchmarks over power consumed illustrates the PolarFire SoC FPGA's low-power advantage.
Built on the award-winning, mid-range, low-power PolarFire FPGA architecture, PolarFire SoC delivers up to 50% lower power than comparable FPGAs.
At 1.3W, PolarFire SoC FPGAs deliver 6,500 CoreMarks while competing SoC FPGAs deliver 0 CoreMarks. PolarFire SoC FPGAs consume 55% lower power at 8,000 CoreMarks.
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PolarFire SoC Datasheet (Earlier DS0147) | 31 Oct 2022 | |
PolarFire SoC MSS Technical Reference Manual | 15 Nov 2023 | |
PolarFire SoC FPGA Register Map | 02 Jan 2024 |
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PolarFire SoC FPGA Engineering Samples (ES) Devices Errata | 16 Jul 2020 | |
PolarFire® SoC FPGA Production Devices Errata | 16 Jan 2024 |
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MPFS250T_MPFS250TS-FCVG484 Package Pin Assignment Table | 30 Jun 2023 | |
MPFS250T_MPFS250TS-FCG1152 Package Pin Assignment Table | 30 Jun 2023 | |
MPFS460T_MPFS460TS-FCG1152 Package Pin Assignment Table | 30 Jun 2023 | |
MPFS160T_MPFS160TS-FCVG484 Package Pin Assignment Table | 30 Jun 2023 | |
MPFS250T_MPFS250TS-FCVG784 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS095T_MPFS095TS-FCVG484 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS025T_MPFS025TS-FCVG484 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS250T_MPFS250TS-FCSG536 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS095T_MPFS095TS-FCSG536 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS095T_MPFS095TS-FCVG784 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS160T_MPFS160TS-FCSG536 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS160T_MPFS160TS-FCVG784 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS095T_MPFS095TS-FCSG325 Package Pin Assignment Table | 02 Jul 2023 | |
MPFS025T_MPFS025TS-FCSG325 Package Pin Assignment Table | 02 Jul 2023 |
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PolarFIre SoC Dedicated IO IBIS Model (AUTO) | 30 Mar 2022 | |
PolarFire SoC Dedicated IO IBIS Model (Industrial) | 30 Mar 2022 | |
PolarFire SoC MSSIO IBIS Model (Industrial) | 14 Dec 2023 | |
PolarFire SoC HSIO IBIS Model (Industrial) | 14 Dec 2023 | |
PolarFire SoC HSIO IBIS Model (Military) | 14 Dec 2023 | |
PolarFire SoC GPIO IBIS Model (Industrial) | 14 Dec 2023 | |
PolarFire SoC Dedicated IO IBIS Model (Military) | 30 Mar 2022 | |
PolarFire SoC GPIO IBIS Model (Military) | 14 Dec 2023 | |
PolarFire SoC HSIO IBIS Model (Auto) | 14 Dec 2023 | |
PolarFire SoC GPIO IBIS Model (Auto) | 14 Dec 2023 | |
PolarFire SoC MSSIO IBIS Model (Auto) | 14 Dec 2023 | |
PolarFire SoC MSSIO IBIS Model (Military) | 14 Dec 2023 | |
PolarFire SoC & PolarFire FPGA IBIS AMI Model | 02 Mar 2022 |
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PolarFire SoC MPFS250 FCV484 TX S-parameter Model | 07 Feb 2023 | |
PolarFire SoC MPFS250 FCV484 RX S-parameter Model | 07 Feb 2023 |
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PolarFire FPGA and PolarFire SoC FPGA Power Estimator User Guide | 09 Dec 2019 | |
PolarFire Family Memory Controller User Guide | 14 Jun 2023 | |
Memory Log Analyzer GUI Installer | 04 Aug 2023 | |
PolarFire , PolarFire SoC and RT PolarFire FPGA Power Estimator | 22 Aug 2023 |
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PolarFire FPGA and SoC FPGA Brochure | 11 Aug 2023 | |
Mi-V RISC-V Ecosystem Brochure | 21 Jan 2018 | |
PolarFire® SoC Product Overview | 21 Dec 2023 |
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PolarFire_SoC_CPU_Performance_Benchmarking_Whitepaper | 30 Mar 2022 | |
PolarFire SoC Linux Boot Time White Paper | 30 Mar 2022 | |
PolarFire SoC FPGA: Application Waypointing | 30 Mar 2022 | |
PolarFire® SoC FPGA: Opus Codec Benchmarking | 30 Mar 2022 | |
PolarFire SoC FPGA: Interrupt Latency and Data Transfer Throughput Measurements | 30 Mar 2022 | |
Measurement of Worst Case Execution Time on PolarFire® SoC FPGA | 18 Jan 2023 |
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PolarFire SoC Icicle Kit Mechanical Drawing | 30 Mar 2022 | |
PolarFire SoC Icicle Kit Schematics | 19 Aug 2020 | |
PolarFire SoC Icicle Kit Board Files | 19 Aug 2020 | |
PolarFire SoC FPGA Board Design Guidelines User Guide | 19 Oct 2023 | |
PolarFire SoC FPGA ICICLE Kit User Guide | 12 Jul 2020 |
PolarFire SoCs are offered with multiple speed grades, temperatures, and package combinations. All temperatures are specified as junction temperatures. The following illustration shows the ordering information.
PolarFire SoC FPGAs feature a multi-core Linux-capable processor that is coherent with the memory subsystem, allowing a versatile mix of deterministic real-time systems and the Linux OS in a single multi-core CPU cluster. PolarFire SoC FPGAs create high-performance and hard real-time systems.
Security starts during silicon manufacturing and continues through system deployment and operations. Our PolarFire SoC FPGAs represent the industry’s most advanced secure, programmable FPGAs for the latest Internet of Things (IoT) applications.
Secure hardware
Design security
Data security
PMP is implemented in each of the PolarFire SoC FPGA’s processor cores. PMP is used to enforce memory access restrictions in conjunction with the machine's privilege state (machine mode, supervisor mode and user mode).
The PolarFire SoC Microprocessor Subsystem (MSS) configurator is a software tool to configure the PolarFire SoC microprocessor subsystem.
Libero SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with our FPGA device families.
SoftConsole is a software development environment for the rapid development of bare metal- and RTOS-based C/C++ software.
The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of the RISC-V ISA and Microchip's PolarFire SoC FPGA and RISC-V soft CPU portfolio.
Visit our technical support portal If you need assistance with your PolarFire SoC FPGA-based design.
Try our discussions forum on our GitHub page. Browse the available database of questions and answers, post your questions and support others in the discussions.
The PolarFire SoC Icicle Kit runs Linux® out of the box and evaluates the microprocessor (MPU) subsystem, FPGA fabric, PCIe®, Gigabit Ethernet, CAN, USB and more.
The PolarFire SoC Video Kit is a full-featured embedded vision development platform targeting secure, reliable and power-efficient vision applications at the edge, including our VectorBlox™ Accelerator SDK and Neural Network IP, and Industrial IoT (IIoT) and automation applications.
Key features:
Key features:
This latest-generation programmer supports the Windows® and Linux® operating systems in conjunction with Libero® SoC Design Suite, FlashPro Express and SmartDebug software.
This fifth-generation programmer supports Windows and Linux environments.
This fourth-generation hardware programmer supports only Windows environments.
This is a CE-compliant production device programmer.
Silicon sculptor adapter modules are package specific. They depend on the product family, but are independent of gate count.
ChipPro is a quick and easy device programming solution for our FPGA devices.
An optional In-House Programming (IHP) service is available if you are purchasing our devices in large volumes.