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Conversion Tools

Migrate Your Designs With Our Conversion Scripts

Driven by the shifting focuses of two major FPGA vendors, many FPGA users are looking to diversify their portfolios. Our FPGAs and SoC FPGAs are strong options for this diversification. To help you convert your existing FPGA designs to our FPGAs, we created Python scripts to help you migrate these existing projects.

The Python scripts analyze existing project files for the project sources and create appropriate FPGA projects in Libero® SoC Design Suite.

Conversion Flow

The conversion flow from the competitor tools is straightforward: based on existing project files, a new project in Libero SoC Design Suite is created. The existing HDL sources are brought into this new project. 

Xilinx® ISE® Design Suite

Xilinx ISE was used to design on older technology, such as Spartan®-6 devices. For migration from Xilinx ISE, read our conversion instructions and use the following conversion script.

Download Conversion Script

Intel® Quartus® Prime

Intel Quartus prime is the development tool for Cyclone® 10, Cyclone V, Cyclone IV, Cyclone V SoC low-cost FPGAs and SoCs and the Arria® mid-range family. Additionally, it supports MAX® II and MAX V CPLDs. For migration from Quartus Prime, read the conversion instructions and download the conversion script.

Download Conversion Script

Videos and Webinars

Support

  1. Make sure that Python is installed on the appropriate machine. This can be Windows®.
  2. Download the appropriate Python script and place it into the project directory.
  3. Open the command line and type the following command:
    python conv_<script_version>.py <options> <file_name_of_project_file>
  4. The scripts create *.tcl-scripts in the current directory plus a log file.
  5. To see available options for the script, run this script alone:
    python conv_<script_version>.py

6. Open Libero SoC Design Suite and select the menu item “Project \ Execute Script…”, select the TCL file that was created by the conversion script and click “Run”. 

7. A Libero SoC Design Suite project is created with the VHDL and Verilog sources of the original project.

8. Exchange the basic components and IPs as shown in the appropriate PowerPoint files.

Additional Resources

FPGA Design Services

Our FPGA design services leverage a world-class team of design experts to expedite your design cycle with guaranteed quality. We tailor our expert services to key vertical and horizontal solutions for Machine Learning (ML), Smart Embedded Vision (SEV), high-speed communications and motor control.

Technical Support 

Browse our support forum or create a support case.