Yes, this is achieved by using some external input pins as frequency banks selectors. Let’s consider the DSC2010 as an example. There are two input pins, pin 5 and pin 6 that are called FS0 and FS1. The four binary combinations of these pins allow selecting one of the four frequency banks of the device. Each frequency bank can be programmed (OTP = One Time Programmed) with a clock frequency that is independent and unrelated to the one of the other three banks.

Similarly, the DSC2110 and DSC2210 use input pin 14 (FS) to select among two frequency banks. The DSC2022 has three frequency select inputs, pins 5, 6 and 7 that can select one among eight frequency banks. This concept is generic and not necessarily restricted to these parts that were picked as examples. Eight frequency banks is the maximum number for the DSC2xxx family.

The output clock frequency is programmed one time (OTP) at the factory. However, frequency bank 0 (and only this specific bank) is shadowed with a nonvolatile memory (RAM). It is therefore possible to temporarily change the three VCO register counters (N, f, M) that set the output frequency. Refer to the DSC2xxx Programming Guide for more details. Again, it is important to note that this is only possible for bank frequency 0, therefore the input frequency select pin(s) must be set in a way to select frequency bank 0 (typically all input pins connected to ground).

The device's data sheet specifies the input logic levels VIH and VIL. These levels apply to all inputs whether they are frequency select pins, output enables or standby, etc.

The DSC2311 will simultaneously provide two frequencies on pins 4 and 5. The device has only one PLL, therefore the two output frequencies must have the VCO frequency as a common multiple.

The DSC400 has four output clocks and two PLLs, therefore two set of outputs can be independent and unrelated to the other set of two.

There are also other clock generators, like the DSC2xxx family, that have frequency select pins. They can provide up to eight selectable frequencies on the clock output pin, depending on the logic levels on the frequency select pins.

As an example, let us consider a 25 MHz carrier and let us assume that its phase noise plot (in the 12 kHz to 20 MHz bandwidth) is known. Let us also assume that one may want to know how different the plot would look like with 10 MHz and 50 MHz carriers.

All the frequency components in the 12 kHz to 20 MHz bandwidth are expressed in dBc/Hz and they scale with the different carrier frequency according to the relationship: 20[dBc/Hz]*log10(frequency/25 MHz)

For frequency = 10 MHz all components shift by -7.96 dB/Hz

For frequency = 50 MHz all components shift by +6.02 dB/Hz

The answer is yes with both. The table below shows an example relative to the DSC1001 device.

We don't recommend using ferrite beads as the ferrite bead may impede the inrush current when the part starts up, and may make the part fail to initialize correctly. A low-value resistor would make a reasonable substitute for the ferrite beads.

It is possible to put the MEMS oscillator devices into latch up via the input control pin (a.k.a. Output Enable or Standby pin). If the voltage on the input control pin goes either ~0.6V above VDD or ~0.6V below GND, then latch up might be initiated. Of course, applying such voltages on the input control pin (pin 1) violates the absolute maximum ratings of the devices.

It's plausible that such voltages could be created unintentionally by the combination of a fast signal generator driving the input control pin and inductance on the trace or cable connecting the signal generator to such a pin. The key behavior produced would be voltage overshoot on the rising and/or falling edges of the signal, as seen at the input control pin. If the magnitude of this overshoot starts to approach ~0.6V, on either rising or falling edges, then that could definitely account for a latch-up condition.

Start-up time, also called tSU in the data sheet, is defined as the time from when VDD reaches 90% of its final value until the first edge on the output clock. The 90% VDD threshold is defined for cases of slow VDD ramp rates, where VDD’s rise time may be significant compared to 1.5ms. There is no output clock until after the PLL has locked and the output frequency is stable.

Enable time, also called tEN in the datasheet, is defined as the time from when the enable pin goes high until the first edge on the output clock. In case the rise time of the enable pin may be significant compared to 1.5 ms, the VIH spec (analogous to the 90% VDD level) specifies the point on the enable pin’s rising edge from which the enable time is measured.

MEMS oscillators and clocks, unlike crystals, have a very stable frequency deviation over the entire temperature range. Frequency deviation in PPM generally rises significantly in crystals when the temperature rises. For MEMS it actually stays pretty flat.

The picture below shows the frequency stability for the DSC1101DI2 at 66.667 MHz, as an example. This is a MEMS oscillator in a 2520 package with nominal ±25 ppm frequency stability.

The short answer is yes.

Data sheet specifications apply to the parts at the time of shipment. The process of soldering the MEMS DSC parts onto a PCB happens after the time of shipment and generally can introduce some modest amount of frequency shift. This solder-down frequency shift will not necessarily be constant across temperature and will, naturally, depend on the parameters of the solder-down process.

The worst frequency shifts are seen when parts are hand soldered onto the PCBs, as opposed to oven-reflowed in accordance with the data sheet’s recommended reflow profile.

The frequency shift due to SMT assembly can depend on the temperature ramp rates and dwell times, amount of solder paste printed, selected solder alloy, and choice of flux paste. It is recommended that the SMT assembler measure their actual reflow profile, preferably with the thermocouple or RTD placed as close to the MEMS device as possible.

Tests have not been conducted in a way that would align with those requirements; therefore, there is no guarantee that the devices will meet either the operating pressure or survival pressure requirement.

However, there is good reason to believe that the parts will not have trouble with these pressure levels. The MEMS devices are packaged using standard QFN materials and processes. During QFN molding, the pressures typically reach the range of 3-10 MPa (430-1430 psi), and this pressure has never been known to cause a device to fail.

The MEMS devices do have a cavity for the MEMS resonator, which is surrounded on all sides by very thick silicon walls, many times thicker than the dimensions of the cavity itself. Because of this, the resonator would theoretically deform by only Angstroms at 1700 psi.

Finally, in accordance with industry standards, all MEMS oscillators and clock devices have passed the pressure cooker (PCT) reliability testing. Also, the devices stand up to military-grade shock and vibration testing.